1. Field of the Invention
The present invention relates generally to a CMOS device and a method of manufacturing the same, and more particularly to a CMOS device with dual polycide gates and a method of manufacturing the same, which is capable of stabilizing gate characteristic of peripheral circuit region.
2. Description of the Prior Art
As well known in the art, a gate of a MOS device has been primarily made from polysilicon. This is because the polysilicon has proper physical characteristics for a gate, such as a high melting point, facilitation of thin film formation, facilitation of a line pattern, stabilization for an oxide atmosphere, and flat surface formation. Further, in the case where the polysilicon is actually applied to MOSFET device, the gate made from the polysilicon implies dopant such as Phosphorus, Arsenic, Boron, etc. and achieves a low resistance.
However, with increasing integration of MOS devices, the line widths and resistance of gates should decrease. In order to achieve low resistance in the fine lines having the narrow width in highly integrated devices, research has been actively undertaken in pursuit of a transitional metal polycide gate, which will have the structure in which a transitional metal-silicide, such as tungsten silicide, titanium silicide, nickel silicide and the like, and polysilicon are stacked instead of an existing polysilicon gate. Especially, the tungsten silicide of the transitional polycides can realize a low resistance on a fine wire width, and satisfies characteristics required as the gate. Thus, the tungsten silicide is expected to have a use in manufacturing large integrated devices.
On the other hand, CMOS device has n+ polysilicon gate formed in all of NMOS and PMOS regions. In this case, there is a problem in that a buried channel is formed by a counter-doping in the PMOS region, which thereby increases a short channel effect.
As an attempt to solve the problem above problem, a method of forming a dual gate has recently been used, in which n+ polysilicon gate is formed in NMOS region and p+ polysilicon gate is formed in PMOS region. The dual gate forming method solves the problem due to the buried channel by forming surface channels in both the NMOS and PMOS regions.
Further, a technology for forming dual polycides, which includes a dual gate forming technology and a polycide gate forming technology grafted together, has been proposed. In order to realize a gate in a highly integrated device having low resistance as well as being able to restrict the short channel effect, the technology for forming dual polycides is necessary.
Hereinafter, a method of manufacturing CMOS device with dual polycide gates according to a conventional art will be described in brief with reference to FIGS. 1A to 1D.
Referring to FIG. 1A, after a device isolation layer 2 is formed in a silicon substrate 1 to define an active region, masking process and ion implant process as well-known are performed to form P-well 3a and N-well 3b on the silicon substrate 1. Then, a gate oxide layer 4 and a polysilicon layer 5 are sequentially formed on the silicon substrate 1 on which the device isolation layer 2 and the wells 3a and 3b. 
Referring to FIG. 1B, the masking and ion implantation processes are performed by known methods to form n+ polysilicon layer 5a and p+ polysilicon layer 5b in the P-well 3a and the N-well 3b, respectively.
Referring to FIG. 1C, a metal silicide layer 6 and a hard mask layer 7 are sequentially formed on polysilicon layers 5a and 5b of which regions are differently doped.
Next, though not shown in detail herewithin, after the hard mask layer 7 is patterned to define the gate region, the metal silicide layer 6, the doped polysilicon layers 5a and 5b, and the gate oxide layer 4 below the patterned hard mask 7 are sequentially etched by using the patterned hard mask 7 as an etching barrier, thereby forming the dual polycide gate including n+ polycide gate 10a for NMOS and p+ polycide gate 10b for PMOS.
Referring to FIG. 1D, an insulating interlayer 8 is formed on the resultant to cover the dual polycide gate. Then, after the insulating interlayer 8 and the hard mask layer 7 are etched to form a bit line contact hole 9, a bit-line 15 contacting the metal silicide layer of the dual polycide gates 10a, 10b is formed on the insulating interlayer 8.
FIG. 1E is a plan view showing a CMOS device manufactured by the method of FIG. 1D, where FIG. 1D is a cross-sectional view taken along the line A-A′ in FIG. 1E. As shown in FIG. 1E, the dual polycide gate 10, i.e. continuous word-lines are transversely arranged, while the bit-lines 15 are longitudinally arranged perpendicularly to the word-lines. The bit-line 15 contacts the corresponding one of the word-lines at the “contact” point as shown FIG. 1E, which more exactly is at the boundary between the NMOS and PMOS.
In the conventional method of forming dual polycide gate as described above, however, a dopant inter-diffusion may likely occur between the NMOS and PMOS in the peripheral circuit region.
Specifically, since the n+ polysilicon layer 5a of the NMOS and the p+ polysilicon layer 5b of PMOS are adjacent to each other in the peripheral circuit region, n type impurity and p type impurity doped in the n+ polysilicon layer 5a and p+ polysilicon layer 5b, respectively, are inter-diffused through the metal silicide layer, so as to cause a counter-doping effect in each gate polysilicon layer in an annealing process for a formation of the interlayer dielectric layer and a succeeding process. Thus, a serious gate depletion effect occurs, in which a sufficient concentration of impurities in each gate polysilicon layer quickly decreases. As a result, the electrical characteristics of the device will degrade (e.g. the threshold voltage changes). Even worse, it may cause a transistor to lose its on/off operational capability.
In addition, the distance between devices in the peripheral circuit region has decreased in the highly integrated semiconductor devices. Therefore, the likelihood of dopant inter-diffusion between the gate of the NMOS and the gate of the PMOS increase as the devices are further highly integrated. It is expected that the gate depletion effect will be more serious due to this dopant inter-diffusion.